1. Field of the Invention
The present invention relates to reference voltage generating circuits of semiconductor memory devices. The present invention relates more particularly to a reference voltage generating circuit employed in a semiconductor device, such as a dynamic random access memory (DRAM), and generating a reference voltage for obtaining an internal power supply voltage (Int.Vcc) from an external power supply voltage (Ext.Vcc).
2. Description of the Background Art
FIG. 8 is a block diagram showing one example of a conventional DRAM. In FIG. 8, the DRAM includes a state detecting circuit 1, a clock generating circuit 2, a gate 3, a row and column address buffer 4, a row decoder 5, a column decoder 6, a sense refresh amplifier and input/output control circuit 7, a memory cell array 8, an input buffer 9, an output buffer 10, an internal voltage-down lowering circuit 11, and a zero-power on reset circuit 15. The DRAM thus structured performs a prescribed operation in response to a column address strobe signal/CAS ("/" indicates an inverted signal), a row address strobe signal/RA;, and a write enable signal /WE, to store data in a prescribed memory cell in memory cell array 8, which corresponds to row and column addresses designated by address signals A0 to A11, and to read out data stored therein. Data to be stored is applied to a memory cell in memory cell array 8 through input buffer 9, and data to be read out is provided through output buffer 10. Internal voltage-down lowering circuit 11 converts an external power supply voltage (Ext.Vcc) down to an internal power supply voltage (Int.Vcc). Zero-power on reset signal generating circuit 15 generates a zero-power on reset signal upon turn-on of the power supply.
FIG. 9 is a schematic diagram showing one example of the internal voltage-down lowering circuit shown in FIG. 8. In FIG. 9, internal voltage-down lowering circuit 11 includes a reference voltage generating circuit 12, a current mirror circuit 13 and i driver 14. Reference voltage generating circuit 12, in response to the external power supply voltage Ext.Vcc, generates a reference voltage, and provides the reference voltage to current mirror circuit 13. Current mirror circuit 13 includes transistors Tr11 to Tr14 and a constant current source J1. By an output of current mirror circuit 13 driven is driver 14. Driver 14 includes a transistor Tr15, and is connected to a constant current source J2.
The operation of internal voltage-down lowering circuit 11 shown in FIG. 9 will now be described. When an internal power supply voltage provided from a node N1 becomes higher than a reference voltage provided from reference voltage generating circuit 14, a value of a current flowing through transistor Tr14 is larger than a value of a current flowing through transistor Tr13. Accordingly, a potential of a node N2 is increased, so that transistor Tr15 of driver 14 is rendered conductive lightly, or non-conductive. This results in decrease or stop of current supply from transistor Tr15 to node N1, reducing the internal power supply voltage to the same level as the reference voltage.
Conversely, when an internal power supply voltage becomes lower than a reference voltage, a value of a current flowing through transistor Tr14 is smaller than that flowing through transistor Tr13, so that a potential of node N2 is reduced, rendering transistor Tr15 conductive. This provides enough current supply from transistor 15 to node N1, increasing the internal power supply voltage up to the same level as the reference voltage.
FIG. 10 is a schematic diagram showing one example of the reference voltage generating circuit shown in FIG. 9. Referring to FIG. 10, the external power supply voltage Ext.Vcc is applied to the source of a p-channel transistor Tr1 through a resistance R1. Transistor Tr1 has its drain connected to the drain and the gate of an n-channel transistor Tr2. The transistor Tr2 has its source grounded. A connection of resistance R1 and the source of transistor Tr1 is connected to the gate of a p-channel transistor Tr3. The source of transistor Tr3 is supplied with the external power supply voltage Ext.Vcc, and the drain of transistor Tr3 is connected to the gate of transistor Tr1 and the drain of an n-channel transistor Tr4. The gate of transistor Tr4 is supplied with the external power supply voltage Ext.Vcc, and the source of transistor Tr4 is grounded.
Transistor Tr2 has its drain connected to the gate of an n-channel transistor Tr6. Transistor Tr6 has its drain connected to the drain and the gate of a p-channel transistor Tr5 and the gate of a p-channel transistor Tr7, and has its source grounded. The sources of transistor Tr5 and the transistor Tr7 are supplied with the external power supply voltage Ext.Vcc. Transistor Tr7 has its drain connected to the source of a p-channel transistor Tr8 having a small current driving power. Transistor Tr8 has its drain and source grounded. A reference voltage is provided from a connection of the drain of transistor Tr7 and the source of transistor Tr8.
The description will now be made on the operation of the conventional reference voltage generating circuit shown in FIG. 10. When the external power supply voltage Ext.Vcc rises to a certain level after turn-on of the power supply, a current I=Vtp/R flows through resistance R1 and transistors Tr1 and Tr2, where Vtp is a threshold voltage of transistor Tr3 and R is a resistance value of resistance R1. Such a current flow causes a current flow through transistors Tr3 and Tr4. Conduction of transistor Tr2 renders also transistor Tr6 conductive, and a current also flows through transistors Tr5 and Tr6. This renders transistor Tr7 conductive, and a current flows through transistors Tr7 and Tr8, so that a reference voltage is provided from the connection of transistors Tr7 and Tr8.
FIG. 11 is a graph showing rising characteristics of the external power supply voltage Ext.Vcc and the internal power supply voltage Int.Vcc provided based on the reference voltage from the reference voltage generating circuit. In the conventional reference voltage generating circuit shown in FIG. 10, when the external power supply voltage Ext.Vcc attains a certain level upon turn-on of the power supply, a current I=Vtn/R flows, so that the reference voltage rapidly rises and the internal power supply voltage Int.Vcc also rises rapidly as shown in FIG. 11, which causes a latch-up.